Automatic Optimization of OpenCL-Based Stencil Codes for FPGAs and Its Evaluation

Tsukasa Endo; Hasitha Muthumala Waidyasooriya; Masanori Hariyama

doi:10.52731/iee.v3.i4.265

Tsukasa Endo Tohoku University
Hasitha Muthumala Waidyasooriya Tohoku University
Masanori Hariyama Tohoku University

DOI: https://doi.org/10.52731/iee.v3.i4.265

Keywords: OpenCL for FPGA, performance tuning, stencil computation, code optimization

Abstract

Recently, C-based OpenCL design environment is proposed to design FPGA (field programmable gate array) accelerators. Although many C-programs can be executed on FPGAs, the best c-code for a CPU may not be the most appropriate one for an FPGA. Users must have some knowledge about computer architecture in order to write a good OpenCL code. To solve this problem, we propose an automatic optimization method. We accurately predict the kernel performance using the log files generated at the initial stage of the compilation. Then we find the optimized FPGA architecture by searching all possible design parameters. We implement the proposed method to find the optimized architecture for stencil computation. According to the results, the design time has been reduced to 4% ∼ 8% of the conventional approach.

Author Biographies

Hasitha Muthumala Waidyasooriya, Tohoku University

Waidyasoriya Hasitha Muthumala is an Assistant Professor in the Graduate School of Information Sciences at Tohoku University. He received the BE degree in information engineering, the MS degree in information sciences, and the PhD degree in information sciences from Tohoku University, Japan, in 2006, 2008, and 2010 respectively. His research interests include reconfigurable computing, processor architectures for big-data applications, and high-level design methodology for VLSIs. He is a member of the IEEE.

Masanori Hariyama, Tohoku University

Masanori Hariyama is a Professor in the Graduate School of Information Sciences at Tohoku University. He received the BE degree in electronic engineering, the MS degree in information sciences, and the PhD degree in information sciences from Tohoku University, Japan, in 1992, 1994, and 1997, respectively. His research interests include real-world applications such as robotics and medical applications, big data applications such as bio-informatics, high-performance computing, VLSI computing for real-world application, high-level design methodology for VLSIs, and reconfigurable computing. He is a member of the IEEE.

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